September 17th, 2025 XYALIS at SPIE Photomask conference 2025 Time to update your Mask Data Preparation flow? This year at the BACUS conference in Monterey, XYALIS introduces an interactive graphical option to ease the adoption of automated frame generation by R&D teams. This complements XYALIS solution which automates the different steps of Mask Data Preparation – Multi Chip Wafer placement, Frame Generation, Mask Layout,...
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July 29th, 2025 Beyond Tapeout: Opening the Dark Side of Mask Data Preparation The transition from chip design to manufacturing is often seen as seamless, but mask data preparation (MDP) remains complex and under-automated. This paper explores MDP challenges and how XYALIS solutions close automation gaps to improve scalability and efficiency. Abstract The transition from design completion (tapeout) to chip fabrication is often presented as seamless, almost magical....
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July 29th, 2025 Leveraging the Advantages of OASIS Files The OASIS® format (Open Artwork System Interchange Standard) was introduced to address the growing complexity of chip design layouts and to overcome the limitations of the aging GDSII format. While it offers immense potential for more compact, efficient layout descriptions, not all OASIS® usage is created equal. OASIS® is highly flexible — which is both its...
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June 12th, 2025 XYALIS at DAC Conference 2025: #booth 2628 3D-ICs, stitching, MPWs, PCMs, multi-patterning, or density management create disruptions, bottlenecks, and inefficiencies in your existing Mask Data Preparation flow? Visit XYALIS @DAC to learn how XYALIS transforms Mask Data Preparation with end-to end automation from specs to masks, and reduces engineering time by up to 40-70% while improving quality and cutting silicon usage by...
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May 6th, 2025 XYALIS at SPIE Photomask conference 2024 Time to update your Mask Data Preparation flow? XYALIS offers cutting-edge MDP solutions tailored to your workflow. Work with our customer oriented team to boost your MDP productivity through customized, production-proven engines that seamlessly integrate with your existing flow. From Multi-Project Wafer placement to frame generation and mask design, our high-speed trade specific engines work...
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October 1st, 2024 XYALIS at DAC Conference 2024: #booth 2516 XYALIS celebrates 26 years of providing state-of-the-art software solutions that increase productivity and reliability of Mask Data Preparation (MDP). With tools ranging from Multi Project Wafer (MPW) placement, frame generation, mask set design, field stitching, mask order form generation, chip and reticle-level dummy fill, and layout manipulation tools, XYALIS automates MDP for the most complex...
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June 24th, 2024 Beyond tape-out: open the dark side XYALIS is excited to announce its participation in the FSiC2024 Free Silicon Conference in Paris, Sorbonne University, on June 20th, 2024. We will be presenting an article titled « Beyond Tape-Out: Exploring the Dark Side. » While the various steps of chip design are well understood, what occurs after the final delivery of GDS2 or OASIS files...
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June 6th, 2024 Minimizing die fracture in 3DIC die integration XYALIS, in collaboration with Mosis, has published a new article in the Journal of Micro/Nanopatterning, Materials, and Metrology about « Minimizing die fracture in 3DIC die integration ». The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a...
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January 3rd, 2024 XYALIS unveils Hartroid: A Strategic Initiative to Counter Hardware Trojans in Defense Systems Grenoble, December 18th 2023 XYALIS is proud to announce, under the European Union Defence Fund, the start of the Hartroid project. Hartroid stands for « Hardware Trojans Identification in Large-Scale integrated circuits ». Hartroid will develop a solution to detect Hardware Trojans (HT) that could leak information or alter the functioning of defense systems. This project has...
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December 19th, 2023 XYALIS at JEVeC conference 2023 in Japan XYALIS will be present at the JEVeC 2023 Day (Japan EDA Venture Liaison Committee) in Kawasaki, November 27th, 2023. We will present our solution for frame generation step that plays a critical role in mask data preparation flow. Abstract Frame generation plays a critical role in mask data preparation flow. This task has become increasingly...
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November 2nd, 2023 XYALIS at SPIE Photomask conference 2023 XYALIS celebrates 25 years of providing state-of-the-art software solutions that increase productivity and reliability of Mask Data Preparation (MDP). With tools ranging from Multi Project Wafer (MPW) placement, frame generation, mask set design, field stitching, mask order form generation, chip and reticle-level dummy fill, and layout manipulation tools, XYALIS automates MDP for the most complex...
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July 18th, 2023 XYALIS at DAC conference 2023 : booth #2455 XYALIS celebrates 25 years of providing state-of-the-art software solutions that increase productivity and reliability of Mask Data Preparation (MDP). With tools ranging from Multi Project Wafer (MPW) placement, frame generation, mask set design, field stitching, mask order form generation, chip and reticle-level dummy fill, and layout manipulation tools, XYALIS automates MDP for the most complex...
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June 9th, 2023 Minimizing die fracture in three-dimensional IC XYALIS, in collaboration with Mosis, has published an article about « Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns ». This result has been presented in the SPIE Advanced Lithography + Patterning, San Jose, California, USA, February 26th – March 2nd, 2023. Abstract The demand for high-performance semiconductor products has...
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May 31st, 2023 Single-pass frame generation for multi-layer 3D circuits XYALIS, in collaboration with ST Microelectronics,  has published an article about a new methodology to automatically build a single-pass frame for multi-layer 3D circuits. This new methodology uses our frame generation tool GOTframe. This result has been presented in the SPIE Photomask Technology Conference, Monterey, California, USA, September 26-29, 2022. Abstract This paper presents a novel...
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May 31st, 2023 Design Driven Dummy Filling XYALIS has set up a new methodology to allow an efficient design driven dummy filling technique. It is used in our dummy filling tool GOTstyle. The result has been presented in a paper during the 2021 International Symposium on Electrical, Electronics and Information Engineering, Seoul, Republic of Korea, February 19 – 21, 2021. Abstract Taking into...
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January 2nd, 2023 November’22: New Release Grenoble – November 30th, 2022 – Today XYALIS unveils a new release bringing powerful improvements in the frame generation engine (GOTframe) and other tools. GOTframe – Frame Assembly Generation Engine Add new ordering items possibilities. Add new centering items capabilities. It enables to center items in the whole scribe of the initial scribe width. Possibility...
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November 30th, 2022 XYALIS at SPIE Photomask 2022 : Single-pass frame generation for multi-layer 3D circuits XYALIS will present a paper about “Single-pass frame generation for multi-layer 3D circuits” at the poster session. This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but are more often made by a backside wafer processing. This proposed flow works in a...
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September 15th, 2022 Geometric based signature – EU patent issuance Grenoble – July 19th, 2022 – XYALIS,  is proud to announce that the European Patent Office (EPO) has granted our European patent EP3740889B1 (June 22, 2022). In this patent, XYALIS provides a new method to compare layout databases using a geometric based signature. Patent abstract The invention concerns a method of generating a digital signature of a geometric design...
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July 18th, 2022 XYALIS at DAC conference 2022 : booth #2455 This year at DAC, XYALIS introduces new exciting features in its Mask Data Preparation field of expertise. Thanks to our frame generation automatic tool latest version, GOTframe, producing ultimate 3D frame chips has never been so easy. Each process options configuration file can be controled by user through new techniques. This makes even easier using...
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May 19th, 2022 April’22: New Release Grenoble – April 19th, 2022 – Today XYALIS unveils a new release bringing powerful improvements in the multi project wafer editor (GOTmuch) and in the frame generation engine (GOTframe). GOTmuch – Multi Project Wafer Editor Number of user defined properties no more limited to 10. Possibility to freeze the placement of some objects and prevent...
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April 19th, 2022 XYALIS at DAC conference 2021 : booth #1407 This year at DAC, XYALIS introduces optimized flows in its two areas of expertise. A new Multi-Project Wafer (MPW) design flow reduces thermal mechanical stress on reticules and improves MPW yield, by leveraging its production-proven Mask Data Preparation tool suite. Thanks to the collaboration with MOSIS and using GOTmuch and GOTfiller, XYALIS has set up a...
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October 19th, 2021 Reducing stress effects on multi-project-wafer reticles Collaborating with MOSIS by using GOTmuch and GOTfiller, XYALIS has set up a new methodology to MPW yield and control CPI. The result has been presented in a paper during the SPIE Advanced Lithography online conference, California, USA, 22-26 february 2021. AbstractWe propose a new method applied on Multi-Project Wafer (MPW) reticles to reduce thermal-mechanical...
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July 21st, 2021 May’21: New Release Grenoble – May 12th, 2021 – Today XYALIS unveils a new release bringing powerful improvements to increase OASIS® reading/writing operations performance. Compression and decompression functions have been optimized so that reading or writing an OASIS® file with cblocks, which is the default behavior, is almost as fast as a straight access. All generated OASIS® files are...
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June 30th, 2021 Geometric based signature – US patent issuance Grenoble – June 29th, 2021 XYALIS,  is proud to announce that the United States Patent and Trademark Office (USPTO) has issued U.S. Patent No. 10,956,368 (March 23, 2021 – application number 16/961,375, equivalent to European patent #WO2019141942). In this patent, XYALIS provides a new method to compare layout databases using a geometric based signature. Patent abstract The...
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May 12th, 2021 Oct’20: New Release Grenoble – October 20th, 2020 – Today XYALIS unveils a new release bringing new powerful features in mask data preparation and dummy filling tools. It includes a python interpreter for maskset manager and dummy fill tool. Also to increase OASIS reading/writing operations performance, compressed blocks (cblock) usage has been greatly improved. GOTmask – Maskset editor tool...
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January 12th, 2021 Spie 2020 – Baccus : Maskset automatic flow This year SPIE Advanced Lithography conference was online. Here is XYALIS presentation that shows a complete maskset automatic flow management with its mask order form in SEMI P10 format. In this presentation, we see how it is easy to set a complete maskset flow.
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October 21st, 2020 MPW Automatic Placement Grenoble – May 4th, 2020 –  The new release of our Multi Project Wafers (MPW) automatic placement engine (GOTcross) for MPW projects brings new powerful features. Here are highlights on these advanced features. The possibility to fill remaining empty space by additional chips has been greatly improved. It is possible to control the increase of the number...
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April 29th, 2020 Mar’20: What’s new in XYALIS tools release Grenoble – March 25th, 2020 – Today XYALIS unveils a new release bringing new powerful features in mask data preparation tools. It includes a python interpreter in GOTmuch, enhanced cut-sets management to improve silicon yield and support for Oracle® database connection. GOTcross We have enhanced cut-sets management. By default, chips must now be centered between the...
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April 1st, 2020 Geometric based signature patent Grenoble – March 28th, 2020 XYALIS is proud to announce that a new patent has been filled (#WO2019141942). In this patent, XYALIS provides a new method to compare layout databases using a geometric based signature. When different teams exchange different versions of the same layout, it is critical to know if the database has changed. The geometric...
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March 24th, 2020 Oct’19: What’s new in XYALIS tools Grenoble – October 15th, 2019 – Thanks to our customers’ feedback, today we unveil a new release. It brings a major improvement in resizing geometries and many small but useful features or improvements in other tools. This goes from graphic user interface enhancement to the addition of new options that greatly simplify the integration in...
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March 24th, 2020 XYALIS at SPIE Photomask 2019: Large Dies Stitching XYALIS will present a paper about « Large dies stitching: a technical and cross-functional teams challenge. » at the poster session. This paper addresses large dies stitching challenges. Stitching is a way to combine several shots “stitched together” to create a die larger than what can fit on a photomask. This technique was originally dedicated to advanced...
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March 24th, 2020 XYALIS at DAC conference 2019 : booth #946 XYALIS introduces a SQL Database Communication Link to further integrate its Mask Data Preparation (MDP) suite in customer design and manufacturing flows. The industry now faces new challenges: complex stitching, 3D chips, MPW or advanced processes. All requiring leading edge tools. Full support for SEMI standards and powerful scripting capabilities make XYALIS MDP tools easy...
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March 23rd, 2020 Covid-19 Grenoble – March 20th, 2020 During this containment period for Covid-19, XYALIS is committed to making sure your team gets support and help as expected, with the quality of service you have come to expect from us. At this time, and following our government instructions, we have made sure all employees work safely from home....
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April 30th, 2019 New Mask Data Prep Distribution Grenoble – April 30th, 2019 – XYALIS unveils it’s latest tools version. This new semiannual distribution bring major enhancements in our MDP flow (Mask Data Preparation) family tools. After adding connections capabilities to any SQL database server, we have added functionalities to face new challenges for 3D chips, stitching, etc. Frame generation, with GOTframe solution, has never...
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April 30th, 2019 Geometry-based signature for layout database comparison Grenoble – May 31st, 2018 – XYALIS unveils a new method to compare layouts databases using a geometry-based signature enabling a safe and fast traceability process. Read the article on TechDesignForum. Exchanges of layout descriptions between teams involved in modern integrated circuit (IC) development and production increase in terms of rate, value, and size. Therefore it...
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March 20th, 2019 XYALIS at SPIE Photomask conference 2017 XYALIS will demonstrate his new Mask Data Preparation flow, including the automatic generation of SEMI P10 Order Forms. Visit us on booth #107 to know more about what we have achieved at the next SPIE Photomoask Technology Conference, September 12-14, 2017, in Monterey, California, USA. Tuesday, September 12 from 10:00 am to 4:00 pm Wednesday, September 13 from 10:00 am...
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December 10th, 2018 XYALIS supports Fahrenheit2451 project Grenoble, France – January 22nd, 2016 – XYALIS and ARNANO’s Fahrenheit 2451 Nanoforms combine art and technology and introduce a new way to preserve precious personal data. After the success of the Kickstarter Fahrenheit 2451 project, the first public sapphire medallions archives have been produced and shipped in december 2015. In each medallion, an image...
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December 10th, 2018 XYALIS new version of GTmuch makes multi-chip modules and multi-project wafers even easier Paris, France – October 1st, 2009 – Xyalis has announced a major upgrade to GTmuch, the company’s graphical tool dedicated to floorplanning and assembly of multiple GDSII databases for Multi-Chip Modules (MCM) and Multi-Project Chips or Wafers (MPC or MPW). At the same time Xyalis has updated its complete suite of GDSII utilities. Designed to reflect...
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November 19th, 2018 New release of our hybrid dummy fill tool, GTstyle GRENOBLE, France, August 21st, 2007 In addition to all exclusive functionnalities such as roughness management or parasitics reduction, GTstyle v2.2 provides new great features:     Full Oasis compatibility     Management of multiple size dummy cells     Automatic interconnection of dummy cells     Management of non orthogonal grids     Critical nets specific keep away distance GTstyle...
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November 19th, 2018 NanoSkills XYALIS is a partner of the NanoSkills project. The NanoSkills project is intended to support the development of sectoral qualifications system and frameworks by definition of qualifications of engineers and technicians in nanotechnologies in terms of learning outcomes to promote transparency and recognition of vocational education and training.
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November 19th, 2018 XYALIS at SPIE BACCUS 2012 XYALIS will be present at the SPIE Photomask/Baccus conference, September 11th-12th 2012 in Monterey, CA, USA Booth # 510. XYALIS, the Mask Data Preparation specialist, will present : GTmask : the powerful and fully automated mask set edition tool. It increases productivity and eliminates the risk of error by automating repetitive manual tasks and by making sure...
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November 19th, 2018 XYALIS at SPIE Advanced Lithography Conference 2013 XYALIS introduces its new highly parallel CMP metal fill engine at the SPIE Advanced Lithography Conference, February 26th-27th 2013 in San Jose, CA, USA – Booth # 205. The new GTstyle release maximizes CMP yield with its highly accurate tile insertion algorithm, now running in parallel for unsurpassed speed and low memory consumption: Patented insertion...
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November 19th, 2018 XYALIS at Date Conference 2013 XYALIS introduces its new highly parallel CMP metal fill engine at the Date Conference, March 19th-21th 2013 in Grenoble, FRANCE – Booth #54. The new GTstyle release maximizes CMP yield with its highly accurate tile insertion algorithm, now running in parallel for unsurpassed speed and low memory consumption: Patented insertion algorithm based on local density...
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November 19th, 2018 XYALIS at SPIE Photomask 2013 XYALIS will be present at the SPIE Photomask conference, September 10th-11th 2013 in Monterey, CA, USA Booth # 510. XYALIS, the Mask Data Preparation specialist, will present : GTframe : automatic frame generator which now includes a visual debugger to solve placement conflicts. GTmask : the powerful and fully automated mask set edition tool. It increases...
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November 19th, 2018 NanoSkills access XYALIS is a partner of the NanoSkills project. The NanoSkills project is intended to support the development of sectoral qualifications system and frameworks by definition of qualifications of engineers and technicians in nanotechnologies in terms of learning outcomes to promote transparency and recognition of vocational education and training. The project is currently running to its...
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November 19th, 2018 XYALIS at DAC Conference 2016 : booth #1918 Shrinking geometries, new manufacturing paradigms, exploding file sizes… It’s time to rethink everything! XYALIS phases in a new generation of tools: from CMP fill to layout manipulation and mask data preparation, redesigned to address the challenges of today’s most advanced processes, with a focus on speed and memory usage. Visit us on booth #1918 to know more...
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November 19th, 2018 XYALIS at DAC conference 2017 : booth #2129 After 2 years, the long migration started in 2015 has just ended and we are proud to announce that the results are beyond our best expectations. Shrinking geometries, new manufacturing paradigms, exploding file sizes… It’s time to rethink everything! XYALIS has just launched a new generation of his tools: from CMP fill to layout manipulation and...
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November 19th, 2018 STMicroelectronics QUALIFIES XYALIS GTSMOOTH OXIDE THICKNESS ESTIMATION TECHNOLOGY Grenoble, France – XYALIS announced today that STMicrolectronics, after several month of validation, has qualified GTsmooth post CMP oxide thickness estimation capabilities. With the deployment of latest advanced process technologies, yield performance degradation due to non-uniform feature density requires an accurate verification of the metal-fill effectiveness prior mask set manufacturing. GTsmooth, introduced last year, offers...
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November 19th, 2018 XYALIS at DAC Conference 2013 XYALIS will show its new highly parallel CMP metal fill engine at the DAC Conference, June 2nd-4th 2013 in Austin, TX, USA – Booth #335. The new GTstyle release maximizes CMP yield with its highly accurate tile insertion algorithm, now running in parallel for unsurpassed speed and low memory consumption: Patented insertion algorithm based on...
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June 4th, 2018 XYALIS at DAC conference 2018 : booth #1610 Leveraging years of leadership in layout finishing, XYALIS introduces a unique geometry-based signature enabling a safe and fast traceability process. It is tailored to handle the multiplicity of design styles and representation standards specific to electronic design while protecting intellectual property during exchanges. As exchanges of layout descriptions between teams involved in modern integrated circuit (IC)...
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August 29th, 2017 XYALIS at SPIE Photomask conference 2016 XYALIS will demonstrate his integrated Mask Data Preparation flow, including the automatic generation of SEMI P10 Order Forms. Visit us on booth #114 to know more about what we have achieved at the next SPIE Photomoask Technology Conference, September 12-14, 2016, in Monterey, California, USA. Monday, September 12 from 10:00 am to 6:00 pm Tuesday, September 13 from 10:00...
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June 21st, 2016 XYALIS announce an Advanced Methodology for Building CMP Models GRENOBLE, France – June 1st, 2007 XYALIS will be able to provide high accuracy thickness measurements on wafers. XYALIS announce today that thanks to « non destructive » nanometric measurement equipment’s, XYALIS is able to build Chemo Mechanical Planarization (CMP) models. These models are used for estimating the critical areas where dummy filling is needed to smooth...
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June 21st, 2016 XYALIS announced today OASIS support for its family of layout finishing tools GRENOBLE, France – November 20th, 2006 With files size explosion at 65nm and 45nm nodes, OASIS becomes a must have alternative for mask prep and layout finishing tasks. OASIS can achieve a compression ratio in the range of 10X for layout files compared to the old GDSII format. OASIS open format also replace a multiplicity...
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June 21st, 2016 XYALIS announced today GTstyle. The next generation tool for Dummies Filling at 65nm and below GRENOBLE, France – May 1st, 2006 XYALIS announced today that it has shipped GTstyle V1.0, its next generation tool for Dummies Filling at 65nm and below. Advanced processes, starting at 65nm and below, require very specific and complex design rules for dummy fills. These new rules cannot be handled by current tools and are necessary...
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June 21st, 2016 XYALIS announce a new release of GTsmooth its density estimator and tiling engine GRENOBLE, France – May 17 th, 2004 XYALIS announced today that it has shipped GTsmooth V2.0, its next generation of model-based estimator and dummy tiles insertion tool. Since 1995, a Chemical-Mechanical Polishing step has been adopted in the process to flatten wafer surface between each metal layer. The approach of inserting “dummy” metal tiles in...
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June 21st, 2016 XYALIS offers unprecedented capabilities with its New Multi-Project Wafer Preparation and management System Grenoble, France – April, 26th, 2004 XYALIS announced today that it has shipped GTmuch V6.0, its next generation Multi-Project-Wafer (MPW) floorplanning and management tool. Mask costs in the latest technologies become a key issue. This leads in new challenges in managing huge and heterogeneous databases. For prototyping, the adoption of MPW program allows dramatic cost...
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June 21st, 2016 XYALIS announces GTsmooth, The First Hybrid Metal-Fill Tool Lyon, France – GTsmooth high performance metal-fill enable designers to integrate CMP (Chemical Mechanical Polishing) effects in their design process XYALIS, the leading provider of layout finishing tools, today announces GTsmooth, the first hybrid metal-fill tool, which combines the benefits of rules- and model-based methods to increase the manufacturing yield of chips and wafers, to limit...
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June 21st, 2016 XYALIS new version of GTmuch makes multi-chip modules and multi-project wafers even easier Grenoble, France October 1st 2001 Xyalis has announced a major upgrade to GTmuch, the company’s graphical tool dedicated to floorplanning and assembly of multiple GDSII databases for Multi-Chip Modules (MCM) and Multi-Project Chips or Wafers (MPC or MPW). At the same time Xyalis has updated its complete suite of GDSII utilities. Designed to reflect feedback...
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June 21st, 2016 DelfMEMS selects XYALIS’s MDP tools XYALIS and DelfMEMS announce that DelfMEMS selected XYALIS’s Mask Data preparation suite to address the challenges of the very sensitive mask design flow required by RF MEMS “This was an exciting challenge to completely automate the Mask Design operation for such a complex and demanding environment as RF MEMS.”  said Philippe Morey-Chaisemartin, XYALIS’s CTO. Thanks...
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June 21st, 2016 XYALIS at DAC Conference 2015 : booth #2606 Multi-Project Wafers have never been that easy! With XYALIS GTmuch, the graphical shuttle editor, mask data preparation teams have been able to cut time to designing multi-chip assemblies. With XYALIS GTcross, the production aware placement engine, they have been able to minimize shuttle production costs. Today, XYALIS introduces WISC, the Web Interface for Shuttle Contributors,...
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June 21st, 2016 XYALIS at DAC conference 2014 XYALIS will unveils GTwatermark which secures your flow by warranting the integrity of your reference layout files, at the DAC Conference, June 2nd-4th 2014 in San Francisco, CA, USA – Booth #403. Have you ever wondered if you were using the right version of your chip layout ? With multiple hand-offs between teams, locations, and companies, it...
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June 21st, 2016 Soft Biz Day award for GTnano On 28 november 2013, XYALIS has won the Soft Biz Day trophy for the best hardware & software integrated solution : GTnano enabling long-term archiving solution . With GTnano, documents can be saved on a  Nanoform, which is a 4 or 8 inch synthetic sapphire or glass disks, for centuries. XYALIS has been chosen among...
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June 21st, 2016 XYALIS and SII NanoTechnology announce strategic collaboration GRENOBLE, France, January 31st, 2011 Chiba, Japan, January 31th, 2011 XYALIS, a leader in Mask Data Preparation software, and SII NanoTechnology, a leader in Photomask Verification software, announced today that they have signed a strategic cooperation agreement to broaden availability of their Photomask Data Preparation solutions, strengthen worldwide support, and develop a unified front-to-back flow...
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June 21st, 2016 XYALIS Brings Cost Reduction To Mask Design GRENOBLE, France, May 26th, 2010 As technology progresses the cost of a complete mask set has been increasing. It is not rare to see a complete mask set reach millions of dollars with the newest technology nodes, a significant part of the overall project cost. It is then critical for design teams, mask data preparation...
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June 21st, 2016 XYALIS marks North American Operations expansion with official opening of an office in San Jose GRENOBLE, France, March 21st, 2008 Xyalis marks North American Operations expansion with official opening of an office in San Jose, California, announces Eric Beisser – CEO of Xyalis. Xyalis, the leader in layout finishing solutions, today officially announced the opening of its North American office and the appointment of Sylvie Hurat as Marketing Account Manager...
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June 21st, 2016 Automatic Mask Pattern Localization In collaboration with KLA-Tencor, XYALIS will present an article during the poster session of the SPIE Advanced Lithography conference in San Jose, California, USA, 21-25 february 2016. Automatic pattern localization across layout database and photolithography mask Abstract Advanced process photolithography masks require more and more controls for registration versus design and critical dimension uniformity (CDU)....
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June 20th, 2016 Nanoform long-term archiving solution XYALIS introduces GTnano enabling long-term archiving solution at the World Trade Center’s Soft Biz Day, 28 november 2013. With GTnano, documents can be saved on a  Nanoform, which is a 4 or 8 inch synthetic sapphire or glass disks, for centuries. With the explosion of digital information, numerical data storage and archiving has become a...
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June 20th, 2016 Nanoform long-term archiving solution XYALIS introduces GTnano enabling long-term archiving solution at the World Trade Center’s Soft Biz Day, 28 november 2013. With GTnano, documents can be saved on a  Nanoform, which is a 4 or 8 inch synthetic sapphire or glass disks, for centuries. With the explosion of digital information, numerical data storage and archiving has become a...
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June 3rd, 2016 XYALIS at DAC 2012 XYALIS will be present at the DAC Conference, June 5th-6th 2012 in San Francisco, CA, USA Booth # 600
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June 3rd, 2016 NanoSkills XYALIS is a partner of the NanoSkills project. The NanoSkills project is intended to support the development of sectoral qualifications system and frameworks by definition of qualifications of engineers and technicians in nanotechnologies in terms of learning outcomes to promote transparency and recognition of vocational education and training.
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June 3rd, 2016 XYALIS at DAC Conference 2013 XYALIS will show its new highly parallel CMP metal fill engine at the DAC Conference, June 2nd-4th 2013 in Austin, TX, USA – Booth #335. The new GTstyle release maximizes CMP yield with its highly accurate tile insertion algorithm, now running in parallel for unsurpassed speed and low memory consumption: Patented insertion algorithm based on...
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June 17th, 2024 XYALIS GTstyle dummy fill engine achieves unsurpassed performance for 28nm highly parallel processor Grenoble, October 29th, 2012 – XYALIS and KALRAY announce that XYALIS GTstyle has successfully addressed the advanced dummy fill challenges of KALRAY’s MPPA-256 manycore processor, designed using state of the art 28nm process. With its complex process rules from both analog parts requiring dedicated dummy fill procedures and large digital areas with timing and race...
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