XYALIS, an Electronic Design Automation (EDA) company, offers specialized tools in the area of Design for Manufacturing. XYALIS main tools includes CMP metal-fill and MCM and MPW layout optimization. These tools brings advanced solution to the most important DFM issues found during the design and the mask preparation. XYALIS tools also increase engineering productivity during tape-out and help reduce time to manufacturing.
XYALIS’ solutions have been developed in cooperation with major semiconductor industry leaders and have been used in production for the most advanced processes.
XYALIS is the only independent company offering a full line of products dedicated to the reticle assembly teams for wafer optimization and management. The current toolset encompasses MPW optimization and placement plus the overall wafer frame management.
XYALIS tools are very robust and has been used in production for more than 25 years at major semiconductor houses without any error.
XYALIS expertise and its success history are quite unique in the EDA industry. From the beginning, the company has focused on Design For Manufacturing tools and solutions to solve complex problems found between design and manufacturing. This area is now called DFM and is popular in the papers and symposiums. Thanks to its founders who have a very deep knowledge and experience in this field XYALIS has been able to innovate and provide new solutions to solve problems faced by engineers today.
XYALIS focuses on three main flows of the layout finishing process:
- Metal filling to address Chemical Mechanical Polishing (CMP) issues
- Mask Data Preparation
- High Performance Computing
Executive Team
Our management team is composed of 4 people totalling over 100 man-year of experience in business development, sales management, software development, semiconductors design and mask preparation.
Eric BEISSER
CEO
30 years experience in management, business development and software development.
Philippe MOREY-CHAISEMARTIN
PhD., Senior Research Fellow
32 years experience in Microelectronics, former Project Manager at STMicroelectronics, associate professor at Grenoble Institute of Technology.
Frederic BRAULT
CTO
Has been working for more than 20 years on HPC software. With a first experience on compilers, OS and libraries dedicated to manycore chips.
Now focuses on leading edge EDA solutions, as CTO of XYALIS.
Farid BENZAKOUR
VP Operations
28 years experience in project management and software development.
2025
OASIS® was designed to overcome GDSII limitations, offering more compact and efficient layout descriptions. However, its flexibility means it can be used poorly, with little gain, or optimally, yielding significant reductions in file size and faster mask data preparation. Drawing on 25 years of experience, XYALIS shares key encoding strategies, common pitfalls, and real-world insights to help design engineers, data prep specialists, and tool developers fully leverage OASIS® capabilities.
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2024
XYALIS unveils Hartroid: A Strategic Initiative to Counter Hardware Trojans in Defense Systems
XYALIS announced, under the European Union Defence Fund, the start of the Hartroid project. Hartroid stands for “Hardware Trojans Identification in Large-Scale integrated circuits”. Hartroid will develop a solution to detect Hardware Trojans (HT) that could leak information or alter the functioning of defense systems.
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2023
XYALIS and Mosis (SPIE 2023) address die fracture in advanced 3D IC packaging, where dies thinned down to 5 µm enable heterogeneous stacks of up to 50 dies but suffer from critical fragility. A crack propagation model is presented alongside an automated MPW reticle placement method that inserts specific polyimide crack-stop patterns. This approach mitigates fracture risk from both wafer sides, improving yield, reliability, and cost in advanced thinning processes.
This result has been presented in the SPIE Advanced Lithography + Patterning, San Jose, California, USA, February 26th – March 2nd, 2023.
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2021
XYALIS, is proud to announce that the United States Patent and Trademark Office (USPTO) has issued U.S. Patent No. 10,956,368 (March 23, 2021 – application number 16/961,375, equivalent to European patent #WO2019141942). In this patent, XYALIS provides a new method to compare layout databases using a geometric based signature.
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2019
XYALIS will present a paper about “Large dies stitching: a technical and cross-functional teams challenge.” at the poster session.
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2016
XYALIS and KLA-Tencor (SPIE 2016) present an automated solution for photolithography mask metrology. Advanced masks require dense, distributed registration and CDU controls, including inside customer dies using non-dedicated patterns, making direct database access essential. The developed Mask Dataprep Station automatically selects measurement targets within large layout databases and generates metrology jobs and design clips. The methodology was validated on advanced production lines, with performance results discussed.
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2012
XYALIS introduces GTmodus, the first commercial tool for Mask Ordering management, based onto a relational Database and a Web Application, and using the industrial SEMI P10 format for data exchange between Semiconductor players (Design centers, FABs) and Maskshops.
2010
XYALIS introduced GTcross, the first Production Yield oriented placement tool for MPWs.
2006
In 2006 XYALIS introduced GTstyle, a new tool for dummies insertion targeting 65nm processes and below. This new tool combines the advantages of the “model-based” approach while maintaining a compatibility with the design rules checks.
2002
In 2002 XYALIS introduced GTsmooth, a model-based CMP process estimator and dummy tiles insertion tool. The approach of inserting “dummy” metal tiles in all empty areas was not satisfactory because it introduced too many parasitics. Traditional methods were not successful in solving this problem and it was necessary to introduce a model based algorithm to get the best results and to minimize the number of inserted tiles while achieving the highest yield.