July 29th, 2025 Beyond Tapeout: Opening the Dark Side of Mask Data Preparation How XYALIS Bridges the Critical Automation Gap from Design to Manufacturing Abstract The transition from design completion (tapeout) to chip fabrication is often presented as seamless, almost magical. However, this perception overlooks a critical reality: a physical mask set must first be manufactured to transfer the layout image onto silicon. Mask data preparation (MDP) remains...
READ MORE

March 3rd, 2023 Minimizing die fracture in three-dimensional IC XYALIS, in collaboration with Mosis, has published an article about “Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns”. This result has been presented in the SPIE Advanced Lithography + Patterning, San Jose, California, USA, February 26th – March 2nd, 2023. Abstract The demand for high-performance semiconductor products has...
READ MORE

January 2nd, 2023 Single-pass frame generation for multi-layer 3D circuits XYALIS, in collaboration with ST Microelectronics,  has published an article about a new methodology to automatically build a single-pass frame for multi-layer 3D circuits.This new methodology uses our frame generation tool GOTframe. This result has been presented in the SPIE Photomask Technology Conference, Monterey, California, USA, September 26-29, 2022. Abstract This paper presents a novel approach...
READ MORE

July 21st, 2021 Design Driven Dummy Filling XYALIS has set up a new methodology to allow an efficient design driven dummy filling technique. It is used in our dummy filling tool GOTstyle. The result has been presented in a paper during the 2021 International Symposium on Electrical, Electronics and Information Engineering, Seoul, Republic of Korea, February 19 – 21, 2021. Abstract Taking into...
READ MORE

March 11th, 2021 Reducing stress effects on multi-project-wafer reticles Collaborating with MOSIS by using GOTmuch and GOTfiller, XYALIS has set up a new methodology to MPW yield and control CPI. The result has been presented in a paper during the SPIE Advanced Lithography online conference, California, USA, 22-26 february 2021. AbstractWe propose a new method applied on Multi-Project Wafer (MPW) reticles to reduce thermal-mechanical...
READ MORE

September 26th, 2019 Large dies stitching: A Technical and Cross-Functional Teams Challenge Philippe Morey, Frederic Brault, Eric Beisser, Farid BenzakourXYALIS – Grenoble – FranceConference: SPIE Photomask Technology + EUV Lithography, 2019, Monterey, California, United States ABSTRACT This paper addresses large dies stitching challenges. Stitching is a way to combine several shots ”stitched together” to create a die larger than what can fit on a photomask. This technique...
READ MORE

June 10th, 2018 Layout Database File Control: The Missing Link By Dr Philippe Morey-Chaisemartin & Frederic Brault XYALIS, France. Published in TechDesign Forum – May 31st 2018 As the exchange of layout descriptions between teams involved in modern integrated circuit (IC) development and production increase in terms of rate, value and size, the need for control and reliability increases as well. While regular integrity control...
READ MORE

March 8th, 2016 Automatic pattern localization across layout database and photolithography mask Philippe Morey(1), Frederic Brault(1), Eric Beisser(1), Oliver Ache(2), Klaus-Dieter Röth(2)1: XYALIS – France2: KLA-Tencor MIE GmbH, GermanyConference: SPIE© Advanced Lithography, 2016, San Jose, California, United States ABSTRACT Advanced process photolithography masks require more and more controls for registration versus design and critical dimension uniformity (CDU). The distribution of the measurement points should be distributed all over...
READ MORE

June 4th, 2015 Is it time to switch to OASIS.MASK ? By Dr Philippe Morey-Chaisemartin & Frederic Brault XYALIS, France. A summary of OASIS ® standard advantages and weaknesses is presented, based on six years of experience with customer databases. A new standard, OASIS.MASK, is being introduced to address the requirements specific to photomask layout representation. This subset of OASIS ® (and as such fully OASIS ® compliant) introduces constraints...
READ MORE

June 28th, 2013 Layout finishing of a 28nm, 3 billions transistors and multi-core processor Philippe Morey, Eric BeisserXYALIS – Grenoble – FranceConference: Photomask and NGL Mask Technology, June, 2013, Yokohama, Japan ABSTRACT Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture, functionalities and timing issues, the layout by itself is a bottleneck due to all the process constraints...
READ MORE

June 27th, 2013 Using a Mask Rule Checker as an Electrical Rule Checker Philippe Morey, Eric BeisserXYALIS – Grenoble – FranceConference: Photomask and NGL Mask Technology, June, 2013, Yokohama, Japan ABSTRACT Design complexity sometimes grows faster than EDA tools performances, and some innovation should be made on the design flow to guarantee the best possible validation in a reasonable time. This was the challenge we were facing for...
READ MORE

October 29th, 2012 Highlights of XYALIS tools in Kalray design flow Context Kalray, a French startup has developed an advanced array processor including 256 cores. This chip has been designed using TSMC 28nm process. Combining huge designs with complex process rules as lead to a bottleneck regarding layout finishing. Typically, dummies generation became a real issue as the final database includes both analog parts, which require...
READ MORE

July 13th, 2012 Industry needs analysis for developing new skills in nano-electronics Philippe Morey-Chaisemartin, CIME-Nanotech, Grenoble, France Slavka Tzanova, Technical University of Sofia, Bulgaria Silvia Schintke, HEIG-VD, Switzerland Danilo Demarchi, Politechnico di Torino, Italy Jack Barokas, Tel Aviv University, Israel Fabian Wleklinski, eWorks, Frankfurt, Germany Jean-Marc Melique, SITELESC, Paris, France Eric Beisser, Xyalis, Grenoble, France Conference: 9th European Workshop on Microelectronics Education EWME’12, At Grenoble, France INTRODUCTION...
READ MORE

July 12th, 2012 CMP Monitoring and Prediction Based Metal Fill Philippe Morey-Chaisemartin (a), Eric Beisser (a), Jean-Claude Marin (b), Lidwine Chaize (b), Pascal Guyader (b), Julien Rosa (b) a: Xyalis – Grenoble – Franceb: STmicroelectronics – Crolles – France Conference: ISQED 2011 – Santa Clara, CA, USA ABSTRACT Nowadays, two different methodologies are used to address the CMP issues. On one hand, we find basic design oriented methods consisting of reaching a minimal...
READ MORE

May 28th, 2012 Yield optimization through MLR techniques Philippe Morey-Chaisemartin, Eric BeisserXyalis, France  Conference: SPIE Photomask 2011, Monterey, CA, USA ABSTRACT Some chip manufacturing steps lead to non-negligible process variation at wafer level. Typically, chemo-mechanical planarization, known as CMP, is a non-homogeneous process and thickness variations can be measured depending on the distance from a specific die to the wafer center. These variations...
READ MORE

January 26th, 2009 European MEDEA+ CRYSTAL Project: “DFM Photomasks inputs for EDA workflow” Task Force Eric Beisser1, Michel Tissier2, David Au3, Stéphane Bonniol4, Patrick Garcia3,Philippe Morey-Chaisemartin1, Dominique Sadran2, Isabelle Servin5, Michel Tabusse4 1 XYALIS sarl., 5 place R. Schuman, BP 1510, 38025 Grenoble cedex 01, France2 Toppan Photomasks France SAS, 118 av. Francis Perrin, 13106 Rousset cedex, France3 Atmel Rousset SAS, av. Olivier Perroy, 13106 Rousset cedex, France4Satin IP Technologies...
READ MORE

August 1st, 2008 From GDSII to OASIS 1 Why switching to OASIS ® ? It’s a banality to say that nowadays, databases for digital chips are more than huge. The physical description of an SOC, encoded in the classical GDSII format, now often goes over 20Gbytes. Files of up to 200Gbytes have been reported by mask houses. Even if storage systems and data...
READ MORE